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So this was an interesting find. We have been working with a rather large VHDL code base, and noticed a huge amount of control logic was being generated during synthesis. It seems that part of this is due to an interesting “feature” of VHDL, or I suppose more exactly of synthesis tools (we saw this with XST and Synplicity).

If you have some case statement, if then else, or switch, etc. Look carefully at signal assignments in each of the various cases. We were not always assigning to each signal in every case. This obviously follows from different cases doing different things.. but here is the tricky part. Clock gating and/or registering of signals is *inferred* for any signal that is not assigned to in all cases!

This can eat up logic fast, and if you are running near capacity of your target device, it can make it even worse, the added logic, clocking, and routing can cause the implementation to balloon. For example targeting an LX110-T, if we went above ~80% utilization, by the time we got through mapping and place&route we were close to 95%. The only way we could account for this was the extra logic used for the inferred control signals.

This may not matter in a lot of designs where you have plenty of room in the part, or maybe you don’t for some reason have a lot of case statements. We ended up refactoring and just assigning a signal to itself or some don’t care value in the other cases.

If you have ever used a Linux distro on an embedded system you know that a bootloader is a necessity. I’ve been working with PetaLinux for the Xilinx MicroBlaze and we have been using FS-boot to launch U-boot and then bring up Peta. However, recently I switched to BlueCat linux to take advantage of the MicroBlaze’s MMU. However, BlueCat doesn’t document a clear way to boot from flash. Below is some simple code to boot BlueCat. Note: the concept was taken from a Xilinx app note.

#include <xparams.h>
#define KDI_FLASH_LOC 0xXXXXXXXX //location of the linux image in flash
#define KDI_DDR_LOC 0xXXXXXXXX //location in DDR that you want your image to end up
#define KDI_LEN 0xXXXXXXXX //length of your image in bytes

main(){

uint8_t* kdi_flash_ptr = (uint8_t*)KDI_FLASH_LOC;
uint8_t* kdi_ddr_ptr = (uint8_t*)KDI_DDR_LOC;

void* laddr;

memcpy(kdi_flash_ptr, kdi_ddr_ptr, KDI_LEN);

laddr = (void*)KDI_DDR_LOC;
(*laddr)();

}

You can use XPS to load your KDI file into flash, and then compile the bootloader into your bitstream, load the FPGA, and you are off!